A multiport network switch in a packet switching network is coupled to stations on the network through its multiple ports. Data sent by one station on the network to one or more other stations on the network are sent through the network switch. The data is provided to the network switch over a shared access medium according to, for example, an Ethernet protocol (IEEE Std. 802.3). The network switch, which receives a data frame at one of its multiple ports, determines a destination network station for the data frame from information contained in the data frame header. Subsequently, the network switch transmits the data from the port or ports connected to the destination network station or stations.
A single Ethernet network switch may have a number of 10/100 Mb/s ports, equaling, for example, 12 ports. The number of end stations connected to the single network switch is limited by the number of ports (i.e., port density) of the network switch. However, users of networking devices demand flexibility and scalability in their networks. To address this need, modular architectures have been developed that enable cascading of identical networking devices or network switch modules. By cascading these devices (or components) in a loop, port density can be readily increased without redesign or development of costly interfaces.
Unfortunately, as the number of cascaded switches increases, so does the system latency (i.e., the aggregate processing delay of the switches). System latency is attributable, in part, to the manner in which the switches store and retrieve the data frames in memory. One traditional memory architecture employs individual, local memories for each cascaded switch, as shown in FIG. 1. In this example, three multiport switches 12a, 12b, and 12c are cascaded together to permit the exchange of data frames received by any one of the switches and subsequent forwarding of the data frames out of a different multiport switch. Each of these switches 12a, 12b, and 12c has a memory interface, 44a, 44b, and 44c, respectively. These memory interfaces 44a, 44b, and 44c enable switches 12a, 12b, and 12c to access their respective memories 601a, 601b, and 601c to write and read the data frames.
For explanation purposes, it is assumed that a data frame is received at a port (i.e., receive port) on switch 12a and that the data frame destination is a node attached to a port on a different switch 12c. Switch 12a first stores the received data frame in memory 601a, and then determines whether to forward the received data frame out of its own port or send it to the next switch in sequence. Because the data frame is not destined to any port of switch 12a, the data frame is retrieved from memory 601 a and sent to the next switch 12b via the cascade port (i.e., the port to which the neighboring switches are connected) of switch 12a. Upon receiving the data frame, switch 12b stores the data frame in memory 601b. Switch 12b then examines the data frame and determines that it should be forwarded to switch 12c. Accordingly, switch 12b forwards the data frame to switch 12c by reading the stored received data frame from memory 601b and sending the data frame out its cascade port. When the data frame arrives at switch 12c, switch 12c writes the data frame into its memory 601c, in similar fashion as the other switches 12a and 12b. At this point, however, switch 12c determines that the data frame should be forwarded out one of its ports, which is connected to the destination node. Hence, switch 12c reads the stored data frame and forwards it out the appropriate port. As evident by this example, the data frame, as it is transferred from switch to switch is stored and read numerous times into the memories of the respective switches. The series of write and read operations disadvantageously imposes costly delay in the switching system.
To address this latency problem, one conventional approach is to employ a common memory among the various switches. FIG. 2 illustrates such a system in which switches 12a, 12b, and 12c share u memory 701 via memory interfaces 44a, 44b, and 44c, respectively. Under this approach, the interfaces 44a, 44b, and 44c are required to have a wider data bus to maintain the speed of read and write accesses as compared to the individual memory arrangement of FIG. 8. For example, the bus width of the memory interfaces 44a, 44b, and 44c may need to increase to 128 bits. The main drawback with this common memory implementation is that the increase in memory bandwidth also results in a proportionate increase in the pin count. An increase in the number of pins disadvantageously requires more area on the circuit board, resulting in greater package cost.